1. Technical Field of the Invention
The present invention relates to circuits and, more particularly, to domino circuits.
2. Background Art
Wide-fanin gates are gates having numerous input ports. Wide-fanin gates are routinely employed on critical delay paths of high-performance datapaths, such as in a microprocessor, digital signal processor, or other semiconductor device. Dynamic/Domino logic techniques have been used to achieve substantially higher performance than are provided by static complementary metal oxide semiconductor (CMOS) technology for wide-fanin gates. For example, referring to FIG. 1, a conventional prior art domino OR gate 10 includes multiple inputs signals A1 . . . An to n-channel field effect transistors (nFET devices) M1-1 . . . M1-n, where n may 2 or more. In a wide-fanin gate, n is considerably greater than 2. Gate 10 also includes a precharge p-channel field effect transistor (pFET device) M2, a keeper pFET device M3, and a static CMOS output stage 14, which is an inverter. During a precharge phase, input signals A1 . . . An are predischarged to Vgnd and a clock signal (Clk) goes low. When Clk goes low, pFET device M2 is turned ON and a domino stage output signal Q is pulled high to Vdd. As signal Q goes high, an inverter 18 turns on pFET device M3 which keeps signal Q high after Clk transitions high, which turns off pFET device M2. During an evaluation phase, if one or more of input signals A1 . . . An goes high, the corresponding nFET device(s) M1-1 . . . M1-n is turned ON pulling signal Q low (Vgnd). When signal Q goes low, an evaluated output signal out at the output of output stage 14 goes high.
Performance is measured by how quickly signal Q goes low and the evaluated output signal goes high. However, the noise immunity of these techniques degrades with process scaling due at least in part to increasing domino-stage transistor leakage current. Recently, strategies to restore back the noise immunity have been proposed: these strategies involve modifying the gate structure by either employing multiple threshold voltages or noise-tolerant pMOS pull-up stages. However, these modifications reduce the performance advantage enjoyed by domino logic techniques over conventional static CMOS techniques.
Accordingly, there is a need for domino circuits with high performance and high noise immunity.